Intel公司Many-core SOC，IC CAD和Verification学术报告会

报告题目：Terascale Computing and What It Means for Validation

报 告 人：Brian A Moore and Dr. Jin Yang Intel公司

报告时间：2006年11月1日 上午 9：30-10：30

报告地点：大阳城国际娱乐官网东主楼10区103室

主办单位：大阳城国际娱乐官网计算机系

Abstract:

Silicon technology scaling will continue to support higher levels of integration, many-core processors architectures and advanced computing trends such as Tera-Scale computing. Each of these trends will require significant advances in design and validation; and higher levels of silicon variation will require more sophisticated validation and test technologies in support of runtime reliability. Intel’s Validation Research Lab is chartered with identifying technology trends and conducting research that is vital to intercepting technology trends on Intel’s strategic roadmap. VRL’s research scope includes pre- and post-silicon validation and in-situ runtime validation. This presentation will provide an overview of the validation problem space and the challenges we are facing as we move forward. It will also look at the types of research that we believe is critical to meet these challenges.

Biography :

Brian A Moore

Corporate Technology Group

Brian A Moore is Director of Validation Research in Intel’s Microprocessor Technology Lab. Moore is responsible for directing validation research for Intel's future microprocessors on technology that spans pre-silicon functional validation, post-silicon validation and in-situ runtime validation to support system reliability.

Moore joined Intel in 1984, working on the design and validation of the iWarp multicomputer and subsequent interconnect components and protocols for Intel supercomputers, including managing the design and validation of the interconnect chips in the TriStar Tera-FLOP Supercomputer. Moore completed a two-year relocation to Israel working on a precursor to the Centrino processor. Recently he managed the Logic Verification Research Group, the Integrated Design and Verification project and, the Methods & Systems and Emerging Technologies research initiatives in Intel’s Design & Test Technology group.

Previous to joining Intel, Moore worked for Westinghouse International on the Fast Flux Test Facility breeder reactor program and for Rockwell International in the Radioactive Waste Isolation Project. He received a B.S.E.E and M.S.E.E. degrees from Brigham Young University in Utah.

Dr. Jin Yang is a Principal Engineer in the Intel Validation Research Lab. Before joining the lab, he was with the Intel Strategic CAD Lab for 10 years. His research primarily focuses on formal methods for hardware design, in particular developing practical and scalable solutions for micro-processor and protocol specification and verification. His earlier contributions on classic symbolic model checking provided key enhancements to Intel FV (formal verification) tools and made impact on several micro-processor projects. His more recent contribution is the invention of GSTE (Generalized Symbolic Trajectory Evaluation), an automated high capacity FV solution for high level specifications that has been applied successfully to the verification of complex designs with thousands of state elements and beyond in micro-processors. This work has also generated considerable interest in the external FV research community. He is currently responsible for researching solutions to address validation challenges in the future many-core SOC design.

Dr. Yang holds five US patents. He received his Ph.D. degree in Computer Science from the University of Texas at Austin in 1997 where his research topic was on the formal specification and verification of real time systems. He received a M. Sc. degree and a B. Sc. degree in Computer Science from Peking University and was a faculty member there in AI before he came to US.