学术报告

Title: Reconfigurable Computing: Opportunities and Challenges

Speaker: Prof. Viktor K. Prasanna（University of Southern California）

Time: 1:30-2:30PM, Dec. 5, 2006

Place: 1-415, FIT Building

Organizer: Research Institute of Information Technology (RIIT), Tsinghua University

Prof. Viktor K. Prasanna is Charles Lee Powell Professor of Computer Engineering in the Ming Hsieh Department of Electrical Engineering and Professor of Computer Science at the University of Southern California. He is also an associate member of the Center for Applied Mathematical Sciences (CAMS) at USC. He served as the Division Director for the Computer Engineering Division during 1994-98. His research interests include parallel and distributed systems including networked sensor systems, embedded systems, configurable architectures and high performance computing.

Dr. Prasanna has published extensively and consulted for industries in the above areas.

He has served on the organizing committees of several international meetings in VLSI computations, parallel computation, and high performance computing. He is the Steering Co-chair of the International Parallel and Distributed Processing Symposium [merged IEEE International Parallel Processing Symposium (IPPS) and the Symposium on Parallel and Distributed Processing (SPDP)] and is the Steering Chair of the International Conference on High Performance Computing (HiPC). He has served on the editorial boards of the Journal of Parallel and Distributed Computing, Proceedings of the IEEE, IEEE Transactions on VLSI Systems, and IEEE Transactions on Parallel and Distributed Systems. He is the Editor-in-Chief of the IEEE Transactions on Computers. He was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is a Fellow of the IEEE. He is a recipient of the 2005 Okawa Foundation Grant.

Abstract

Reconfigurable devices and systems have evolved over the past decade. Recently, several state of the art high end platforms have incorporated FPGAs for application acceleration. This talk explores algorithmic optimizations for accelerating a wide variety of applications on such systems. We discuss early theoretical underpinnings and illustrate the performance improvements for embedded as well as scientific computing on such platforms. We develop algorithmic optimizations for such systems and demonstrate the suitability of FPGAs for floating point intensive computations. We discuss the design of a BLAS library for such systems. The performance of FPGAs is also compared against those of state-of-the-art embedded processors, general purpose processors, and DSPs for floating point intensive applications. We conclude by highlighting the challenges in further exploiting this technology for application acceleration.